[PJVol]

How do you manage to reach 1ns improvement? mine pretty much like yours but with 5600 non X

It's too long ago... )
Technically speaking -1ns kinda fit 200 MHz higher max boost of "X", but this only applicable to AIDA results from the same PC. Comparing scores from different systems makes almost no sense.

P.S. Just looked at your screenshot and I was "What the ...". Are you sure you didn't mix up RDWR and CWL timings? ))
tCWL is always 0-2 ck below tCL, tRDWR = (tCL - tCWL) + 8

 

[The_King]

P.S. Just looked at your screenshot and I was "What the ...". Are you sure you didn't mix up RDWR and CWL timings? ))
tCWL is always 0-2 ck below tCL, tRDWR = (tCL - tCWL) + 8

I was thinking the same thing.

I have some test data from a few years back for 4000 CL15 with my 5600. This was on Windows 10. With Windows 11 latency is all terrible for me now.

 

[alalalalan01]

It's too long ago... )
Technically speaking -1ns kinda fit 200 MHz higher max boost of "X", but this only applicable to AIDA results from the same PC. Comparing scores from different systems makes almost no sense.

P.S. Just looked at your screenshot and I was "What the ...". Are you sure you didn't mix up RDWR and CWL timings? ))
tCWL is always 0-2 ck below tCL, tRDWR = (tCL - tCWL) + 8

Ikr 200mhz difference between "X" i'm not comparing different machine but asking yours, here summary if you had misunderstanding
yours:
4066mhz 15-8-16-16-32-48-1T = 49.7ns
4200mhz 16-8-16-16-32-48-2T = 48.8ns

mine:
4066mhz 15-8-16-13-26-39-1T = 50.3ns
4200mhz 16-8-16-13-26-39-1T = 50.1ns

The point is how do you get latency so low compared to your 4066 while also running 4200 at CR 2T and even at those frequency but with loosen tCL

tCWL give more bandwidth for me around 2% than lower tRDWR, here's some little explanation

 

[PJVol]

The point is how do you get latency so low compared to your 4066 while also running 4200 at CR 2T and even at those frequency but with loosen tCL

Ah, I see. Well, Idk why you couldn't reduce the latency going from 4066-15-16 to 4200-16-16 by at least half a ns.

tCWL give more bandwidth for me around 2% than lower tRDWR

Curious to look at some test results in practice.

 

[alalalalan01]

Ah, I see. Well, Idk why you couldn't reduce the latency going from 4066-15-16 to 4200-16-16 by at least half a ns.

I saw your 4200 soc at 1.25v isn't that too high as well to feed 1.050v iod and 1.1v ccd? for me vsoc and vddp does nothing except ccd for reduce jitter and iod to fix usb port etc. I also never really play with cad bus, odt impediance or resistance even Setup, so idk why latency won't reduce.

Curious to look at some test results in practice.

Try trade them really and you can lower tWRRD for higher tRDWR or you can set lowest tCWL and leave third timings RDWR and WRRD auto it will train it self. Pick tm5 config you like and look at maximum bandwidth on hwinfo64, around 10 mins or 3 cycles sometimes you will find consistent result.

 

[ManniX-ITA]

I saw your 5600x running 4066c15 tRCD 16 and 4200c16 tRCD 16. How do you manage to reach 1ns improvement? mine pretty much like yours but with 5600 non X running 4066c15 tRCD 16 average around 50.3ns sometimes 50ns and tried with 4200c16 tRCD 16 only get like 50.1ns with imc vsoc 1.2v vddp 1.0v ccd 1.05v iod 1.1v and try many things the latency between 4066mhz and 4200mhz are prety much the same except 4200mhz has slightly more bandwidth.

Thanks for sharing it, very interesting. Will try to play and check with TM5/HWInfo.
Something new to play with on DDR4 it's very rare these days

I saw your 4200 soc at 1.25v isn't that too high as well to feed 1.050v iod and 1.1v ccd? for me vsoc and vddp does nothing except ccd for reduce jitter and iod to fix usb port etc.

VSOC effect is very different per sample, I need 1.20V on my 5950X for something that other samples can do with 1.10V or 1.15V.

I also never really play with cad bus, odt impediance or resistance even Setup, so idk why latency won't reduce.

Why not? If you are looking to save even an half ns it may be worth to play with them.
If you have a lot of time to spend on it you can do some nice things with SR sticks.

There is really an overwhelming amount of things that can influence AIDA64 latency by 1ns; some boards/AGESA combination can just give you a 1ns advantage with exactly the same configuration of others.
If I recall just disabling CPPC Preferred cores gives you a +1ns? Not sure.

Did you try a profile at CL14?
Cause for whatever reason, my Unify-X with my 5950X against exactly the same configuration, goes slower at CL15.
While profiles at CL14 and CL16 runs with same latency.
Guess my IMC simply doesn't like CL15, maybe it's worth a try.

 

[alalalalan01]

VSOC effect is very different per sample, I need 1.20V on my 5950X for something that other samples can do with 1.10V or 1.15V.

I tried running lowest before WHEA then running lowest after IOD requirment after all that i don't find any perfromance impact whatsoever.

Why not? If you are looking to save even an half ns it may be worth to play with them.
If you have a lot of time to spend on it you can do some nice things with SR sticks.

I don't even know where to begin with because so many variable and combination will get different result that hard to tell. Like testing procodt then try with higher and lower drive strenght combination also i still don't how cad bus setup works only 56 magic number. If somehow managage to get improvement but it's unstabe then i prob have no idea where it wrong.

There is really an overwhelming amount of things that can influence AIDA64 latency by 1ns; some boards/AGESA combination can just give you a 1ns advantage with exactly the same configuration of others.
If I recall just disabling CPPC Preferred cores gives you a +1ns? Not sure.

Soon when i heard this i went to test 3 CPPC combination. CPPC on + preferred off was the reccomendation and its give constistent latency again i tried with CPPC off + preferred off i got highest fps on benchmark. Anyway thanks for i that i learn new things as well.

Did you try a profile at CL14?
Cause for whatever reason, my Unify-X with my 5950X against exactly the same configuration, goes slower at CL15.
While profiles at CL14 and CL16 runs with same latency.
Guess my IMC simply doesn't like CL15, maybe it's worth a try.

I never try CL14 above 4000mhz because have to put tons of voltage on it and the improvement just a little. What benefit most is tRCDRD what i learn it's way more important than tCL, like 1 tick tRCD equal to 4+ tick tCL.

Also tRCD it's the hardest one to keep stable because really temperature sensitive and there's negative voltage scaling, at that point where people stop tuning b die because of tRCD rollover.

I think i found the reason why 2T has same or better performance than 1T. It's tPHYDRL that influence to latency. At 2T it's on 26 while 1T are 28. Tried changing with vsoc, vddp, pll its still train the same. Also the board to begin with can't even boot from 3733mhz with 1T unless i put cad bus setup on it. So it just the motherboard is probably the limiting factor.

 

[ManniX-ITA]

I tried running lowest before WHEA then running lowest after IOD requirment after all that i don't find any perfromance impact whatsoever.

Seems to be a very nice sample

I don't even know where to begin with because so many variable and combination will get different result that hard to tell. Like testing procodt then try with higher and lower drive strenght combination also i still don't how cad bus setup works only 56 magic number. If somehow managage to get improvement but it's unstabe then i prob have no idea where it wrong.

If you read this thread you'll find a lot of hints and previous experience.
Once you end up in a stall with a configuration you can't get stable or doesn't boot you start experimenting from what was successful by others and try to work on it till you find something that works for you.

I never try CL14 above 4000mhz because have to put tons of voltage on it and the improvement just a little. What benefit most is tRCDRD what i learn it's way more important than tCL, like 1 tick tRCD equal to 4+ tick tCL.

Also tRCD it's the hardest one to keep stable because really temperature sensitive and there's negative voltage scaling, at that point where people stop tuning b die because of tRCD rollover.

Sorry I don't think anything of this matches my experience

Yes lowering tCL requires a lot of voltage, it's the most important primary and it has a massive impact in almost everything else; I don't see how RCDRD could be more important, it's the 2nd most important but not close to CL.
The 1 to 4+ tick between RCD and CL doesn't ring any bell, what is the tick?

tRCD is temperature and bin quality dependent; there's an hard ceiling, not really negative voltage scaling.
I have never seen people stopping tuning because of it; you work around it and find creative solutions or just leave it as it is and optimize the rest.

I think i found the reason why 2T has same or better performance than 1T. It's tPHYDRL that influence to latency. At 2T it's on 26 while 1T are 28. Tried changing with vsoc, vddp, pll its still train the same.

There are years of discussions about tPHYDRL here and how to get it at 26 with different configurations.
I don't remember anymore the details, changes based on tCL, SR/DR, VDDP, etc.
But as far as I remember the impact on latency, by purely tPHYDRL, is almost negligible.

Also the board to begin with can't even boot from 3733mhz with 1T unless i put cad bus setup on it. So it just the motherboard is probably the limiting factor.

Maybe one of the factors but that's something pretty normal; could be the IMC and/or the DIMM as well. That's why you may need to play with the termination to avoid the Setup delay.

With the Viper 4400 SR but get pure 1T working over 4200 on this board with the 5600G I always had to use exotic stuff like 7/1/5 or 7/1/6 and lower ProcODT with ClkDrvStr either at 30 or 60/120:

At these very high frequencies a finetuning of setup timings helped me find stability.

Not sure what is your goal, what are you pursuing?
Seems to me you just want a good latency, is that right?

Cause if you just aim for a good latency you are probably going to end up with something that benches well in that but generally performs much worse.
If you aim to have the best overall performances, meaning consistent and reliable performances in all applications and not just some, you need to focus on a clean cycle.
A clean cycle will have good latency but also bandwidth in all scenarios, reads, writes and mixed operations.

I suggest you look for the extensive knowledge shared here by Veii, filter for his posts:

https://www.overclock.net/threads/asrock-x370-taichi-overclocking-thread.1627407/page-353?post_id=28246564#post-28246564

If you focus on the whole picture you will get overall better performances, higher CPU boost clocks and IPC, and maybe also re-gain something on latency.

 

[alalalalan01]

If you read this thread you'll find a lot of hints and previous experience.
Once you end up in a stall with a configuration you can't get stable or doesn't boot you start experimenting from what was successful by others and try to work on it till you find something that works for you.

it took time i guess before i move new pc platform

Sorry I don't think anything of this matches my experience

Yes lowering tCL requires a lot of voltage, it's the most important primary and it has a massive impact in almost everything else; I don't see how RCDRD could be more important, it's the 2nd most important but not close to CL.
The 1 to 4+ tick between RCD and CL doesn't ring any bell, what is the tick?

tRCD is temperature and bin quality dependent; there's an hard ceiling, not really negative voltage scaling.
I have never seen people stopping tuning because of it; you work around it and find creative solutions or just leave it as it is and optimize the rest.

The tick lowering number of tCL, tRCD, tRP, tRAS (16-15-16-21), its way better than (15-16-16-21).
Yes it's bin dependant. For pre-2019 B die, it's quite rare to get tRCD scaling even to 1.50v. Most samples start scaling negatively somewhere in the 1.4v range and some even below 1.4v.
For 2020+ B die, it's usually something like 1.48-1.58v, some rare samples scale as high as 1.67v.
(quote from Eden)
Mine start scales at 1.54v-1.55v in bios, on this board it shows 1.56v-1.57v at 4200c16 i can keep tRCD 16 max 50C, i can go lower to tRCD 15 if i keep below 45C for a while of what suggested under 40C, i stop because i don't want to hear 100% fans noise running all the time.
Althought Buildzoid and people who make guides also mention tCL not really important maybe you should try like 20-15-15 to see the difference?

There are years of discussions about tPHYDRL here and how to get it at 26 with different configurations.
I don't remember anymore the details, changes based on tCL, SR/DR, VDDP, etc.
But as far as I remember the impact on latency, by purely tPHYDRL, is almost negligible.

What suprisingly most disscusion about tPHY and latency impact information i could find was here and also the person i'm questioning with pretty much same setup was here and that hopefully i could get some information from so i could implement, but i guess i found the answer i need and probably need more testing something else.

Maybe one of the factors but that's something pretty normal; could be the IMC and/or the DIMM as well. That's why you may need to play with the termination to avoid the Setup delay.

With the Viper 4400 SR but get pure 1T working over 4200 on this board with the 5600G I always had to use exotic stuff like 7/1/5 or 7/1/6 and lower ProcODT with ClkDrvStr either at 30 or 60/120:

View attachment 2732117

At these very high frequencies a finetuning of setup timings helped me find stability.

Yeah it could be the IMC even i can boot FCLK 2166 but regression start at FCLK 2133 so i settle at 2100 no WHEA and error from overnight test so far but next time will play with terminations.
Do you prefer running desync? does performance penaly compared 1:1?

Not sure what is your goal, what are you pursuing?
Seems to me you just want a good latency, is that right?

Cause if you just aim for a good latency you are probably going to end up with something that benches well in that but generally performs much worse.
If you aim to have the best overall performances, meaning consistent and reliable performances in all applications and not just some, you need to focus on a clean cycle.
A clean cycle will have good latency but also bandwidth in all scenarios, reads, writes and mixed operations.

Preferable latency over bandwidth because things i run much demand from that. For now i just leave this auto for ovenight test, so far lowest 49.7ns mostly it just stay at 50ns

I suggest you look for the extensive knowledge shared here by Veii, filter for his posts:
https://www.overclock.net/threads/a...x370-taichi-overclocking-thread.1627407/page-353?post_id=28246564#post-28246564

If you focus on the whole picture you will get overall better performances, higher CPU boost clocks and IPC, and maybe also re-gain something on latency.

Oh that information already old isn't it? i think i follow something that wasn't include meme timing rules:

 

[ManniX-ITA]

The tick lowering number of tCL, tRCD, tRP, tRAS (16-15-16-21), its way better than (15-16-16-21).

I understand what do you mean but in my opinion it's not necessarily true; it all depends on what you can do with the other timings.
It's more often better to lower tCL instead of tRCD because you have less limits and gives you much more headroom and solutions to play with the other timings.

Yes it's bin dependant. For pre-2019 B die, it's quite rare to get tRCD scaling even to 1.50v. Most samples start scaling negatively somewhere in the 1.4v range and some even below 1.4v.
For 2020+ B die, it's usually something like 1.48-1.58v, some rare samples scale as high as 1.67v.
(quote from Eden)
Mine start scales at 1.54v-1.55v in bios, on this board it shows 1.56v-1.57v at 4200c16 i can keep tRCD 16 max 50C, i can go lower to tRCD 15 if i keep below 45C for a while of what suggested under 40C, i stop because i don't want to hear 100% fans noise running all the time.
Althought Buildzoid and people who make guides also mention tCL not really important maybe you should try like 20-15-15 to see the difference?

What I meant is that there's no negative voltage scaling, not that there's no voltage scaling.
If it doesn't improve with voltage scaling then it's because you have hit a hard limit with voltage/temperature.

I don't remember guides that are mentioning tCL not being very important, maybe it's a limit of my knowledge.
About Buildzoid I love his streams on memory OC, I've seen countless.
But honestly I wouldn't ask him to OC my memory
What he tries to achieve usually is just booting the memory at the highest clock, regardless of anything else.

You are right not to stress thermally the DIMM for tRCD; it's a blackhole for reliability.
Could pass 24h of TM5 and weeks later erroring like hell due to a couple °C more of ambient.

Do you prefer running desync? does performance penaly compared 1:1?

Absolutely not, that's only for benching with y-cruncher.
In general there's a massive performance penalty, only a few things are faster.

Oh that information already old isn't it? i think i follow something that wasn't include meme timing rules:

Yes it was just the first bookmark I've found, suitable for Filter by user.

Preferable latency over bandwidth because things i run much demand from that. For now i just leave this auto for ovenight test, so far lowest 49.7ns mostly it just stay at 50ns

It's not bad, honest profile, I would:

• use tRFC2/4 scaled with calculator: 270/201/124
• try tWRWRSCL at 2 instead of 4 (but I don't think will help with latency, more bandwidth)
• check if you can reduce ProcODT to 32, it will help with latency

 

[Royce5800x]

[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

AM4 Ryzen Memory Stability Thread Please try to remember the following Clarify what platform and CPU you are speaking about when asking a particular question or speaking about your experience. Quote the user you are replying to when replying. When posting stability results, be sure to...

www.overclock.net

https://www.overclock.net/posts/28735943/

If you go back a long way in the thread, Veii talks about the CAD and RTT. My kit likes the 40 on ClkDrvStr, and I spent a ridiculous amount of time screwing with IF voltage setup to find that I had it close enough in the first place. I have dual rank sticks, and my CPU/motherboard throw WHEA above 1900 regardless of how I set the voltages

If you do go back in the thread, there is one guy Kaliz? that was going with very high speed RAM, but may have been using a G-series CPU, which may be helpful or not.

 

[lande]

Hey! I'm running my CWL at 10, so i decided to check if it would be beneficial to loosen it and tighten RDWR. For some reason I can't raise CWL to 14 or 15 without corrupting bios. I previously tuned this setup at CL16 and decided on CLW10, but now that I managed to get it running at CL15, the CLW seems stuck where it is. I'm suspecting the controller is not actually running CWL10. Any ideas on what's going on?

 

[alalalalan01]

Hey! I'm running my CWL at 10, so i decided to check if it would be beneficial to loosen it and tighten RDWR. For some reason I can't raise CWL to 14 or 15 without corrupting bios. I previously tuned this setup at CL16 and decided on CLW10, but now that I managed to get it running at CL15, the CLW seems stuck where it is. I'm suspecting the controller is not actually running CWL10. Any ideas on what's going on?
View attachment 2732458

Set tCL you desired and set tRDWR and tWRRD auto. Boot and check each dimm if tWRRD mismatch

 

[S.Maelstrom]

Cheers everyone! First of all I'd like to thank all the contributors to this thread, firm handshakes all around. It is thanks to you that I've managed to make any progress in tuning my RAM.
Now, I'm posting this in the hope that someone will share suggestions as to how one'd proceed with this setup of mine, which includes:

• Crosshair VI Hero with custom 8801 bios (courtesy of @LiimaSmurffi)
• 5700X3D overclocked to 4250mhz and -30 all core CO, stable
• 4 sticks of 3733cl17 Patriot Viper Steel (PVS416G373C7K), H8C, one 2x8 set in A1-A2, another in B1-B2 (thanks @Royce5800x).

So far I've arrived at this config, but I'm totally out of my depth and unsure if there are even any gains to be had. The thing is, I spent about 6 months running 16-21-22-42-66 @3733 with passmark uncached read score of 30500 and write bordering on 20000. The latency test would occasionally return 39, but the rest of the results were not to my liking.

The current config has been stable through 1h of OCCT cpu+ram, 1h OCCT memory, 7h TM5 anta777, 3h TM5 1usmus. VDIMM is set to 1.37000 in UEFI, but the readouts fluctuate between 1.3952v and 1.417v, with 12h average of 1.400v according to HWinfo64.

 

[Royce5800x]

I would think VDDP to .95 should help as 1V there seems too high.

Are you forcing the RTT values in BIOS, or is that on AUTO?

 

[S.Maelstrom]

I would think VDDP to .95 should help as 1V there seems too high.

Are you forcing the RTT values in BIOS, or is that on AUTO?

VDDP used to be 1.09v on auto until I manually set it to 1v just to follow the general recommendations. It didn't do anything for stability when I was trying for 16-20-20-36-56 and loosening up from there. I'll try lowering it to .95 no problem (UPD: done, in fact, I've also set VDDG_CCD to .95 and VDDG_IOD to 1.0, monitoring results now)

Yes, I'm forcing RTT values that I got from this guide on HardwareLuxx.

 

[Kluge156]

Hey all! New OCer and have been poking around the forum and tuning my kit on and off for the last few months. Wanna get some opinions on what ive got so far. Im running a 5800x on a gigabyte aorus pro wifi rev 1.1 board with 4x8 3600 16-16-16-36 ( g.skill f4-3600c16q2-64gakz).

current timings, stable in testmem 1usmus for a couple hours (didnt grab a screenshot of that mb)

i have cooling on my sticks(140mm fan sitting on gpu and top mounted 140mm above the sticks) and highest temps ive seen on them after a long gaming sesh is 42 maybe 43C.

i absolutely cant for the life of me get flat 16s at 3800. ive tried up to 1.65v, no dice. testmem spits errors. maybe i just have mid bdie and accept my lot? any room for improvement here?

 

[Royce5800x]

VDDP used to be 1.09v on auto until I manually set it to 1v just to follow the general recommendations. It didn't do anything for stability when I was trying for 16-20-20-36-56 and loosening up from there. I'll try lowering it to .95 no problem (UPD: done, in fact, I've also set VDDG_CCD to .95 and VDDG_IOD to 1.0, monitoring results now)

Yes, I'm forcing RTT values that I got from this guide on HardwareLuxx.

The 4xSR setup is very similar to the 2xDR setup. Those guides are more for a T-topology, where most boards are daisy chain. I am not sure with your board what it would choose, but I had a lot of difficulty trying with the same setups on 4xSR. The 7/3/1 is what my board was detecting and worked much better with the kit I was playing

 

[Royce5800x]

Hey all! New OCer and have been poking around the forum and tuning my kit on and off for the last few months. Wanna get some opinions on what ive got so far. Im running a 5800x on a gigabyte aorus pro wifi rev 1.1 board with 4x8 3600 16-16-16-36 ( g.skill f4-3600c16q2-64gakz).

current timings, stable in testmem 1usmus for a couple hours (didnt grab a screenshot of that mb)
View attachment 2733430

i have cooling on my sticks(140mm fan sitting on gpu and top mounted 140mm above the sticks) and highest temps ive seen on them after a long gaming sesh is 42 maybe 43C.
View attachment 2733433
i absolutely cant for the life of me get flat 16s at 3800. ive tried up to 1.65v, no dice. testmem spits errors. maybe i just have mid bdie and accept my lot? any room for improvement here?

Maybe loosen up all the secondary timings, and work on getting the primaries right first. I also had better results with a 40 on ClkDrvStr, seems to reduce the amount of voltage needed. My 2x16 kit needs 1.46 for straight 15's

Thinking you may benefit from better DIMM placement as well. Some recommend going through them all 1 by 1 to figure which boots to the highest clock speed and scale them fastest farthest from the CPU socket

 

[Kluge156]

Maybe loosen up all the secondary timings, and work on getting the primaries right first. I also had better results with a 40 on ClkDrvStr, seems to reduce the amount of voltage needed. My 2x16 kit needs 1.46 for straight 15's

Thinking you may benefit from better DIMM placement as well. Some recommend going through them all 1 by 1 to figure which boots to the highest clock speed and scale them fastest farthest from the CPU socket

when testing DIMM placement which slot is best to test in? Would it be based on what my motherboard's recommends for single channel config? Also, when loosening out secondaries to figure out primary timings, should i just leave them all on auto or plug in loose timings manually?